Electrochemical Migration (ECM) Testing

Testing for electrochemical migration (ECM) would occur in the case of a field failure return. Metal migration between isolated conductors on a completed printed circuit assembly may produce electrical shorts.

Why does this growth occur and what do you need to look for? Basically, we need to know if our assemblies are “dirty.” By dirty, we mean littered with ions. Ions on printed circuit assembly surfaces can cause short circuits. In simple terms, shorts occur when the space between the conductors is bridged by dendrites formed by re-deposited metal ions. This metal migration is best described by IPC as a reverse plating of the conductors in the presence of ions, water and an electrical potential.

Electrochemical Migration Testing and Soldering Products

Electrochemical migration testing may also be utilized to assess a soldering product’s propensity to contribute to the development of leakage current across electrically isolated circuits. We want to be sure we select IPC or Bellcore qualified soldering products that have passed the ECM testing. Examples of products requiring ECM testing are flux-containing solders and solder masks.

Product IPC-CC-830 MIL-I-46058
Soldering Flux IPC J-STD-004; IPC-TM-650 methods 2.6.14.1; Bellcore GR-78-CORE IPC-B-25A
Solder Mask IPC-SM-840; IPC-TM-650 method 2.6.14 IPC-B-25A

Dendritic Growth

When dendritic growth occurs in the field, it is often difficult to diagnose. Because dendrites are fragile, they have a low current carrying capacity. This fact causes these short circuits to form and burn off repeatedly. Typically, a full root cause failure analysis is needed by an experienced test laboratory. Trace Laboratories has all of the resources and experience necessary to discuss, develop, perform, and interpret ECM testing and its results.

Analyzing and Predicting Electrochemical Migration Failures on Field Failure Returns

Overview

Electrochemical Migration has been discovered on your assembly after burn-in, or worse yet, on a product returned from the field. A leakage current developed between two isolated circuits and a short circuit occurred. You build IPC Class 2, Dedicated Service Electronic, and Class 3, High Performance Electronic, Products, so this type of failure is of great concern to your company. You want to know if this is an isolated incident or is your whole lot in danger of failing in the field? This article outlines options that are available to analyze this specific lot of assemblies and steps that can be taken to prevent ECM failures on future lots. IPC J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies1, is used as a guideline in preparing a customized test procedure. This article outlines exact procedures that may be used to assess non-failed assemblies for ECM potential.

Case studies are included. The general procedure is as follows: Monitoring points connected to the area of concern are isolated, often by removing components or cutting other traces and wires are soldered. The assemblies are placed in a temperature/humidity chamber and a bias is applied across the suspect location. The resistance between these isolated points is monitored for sudden or slow drops that are indicative of leakage current development or dendritic growth. If ECM development is observed on these assemblies from the same lot, the entire lot should be considered at risk.

Why does Electrochemical Migration occur?

Metal migration between isolated conductors on a completed printed circuit assembly may produce electrical shorts. Why does this growth occur and what do you need to look for? Basically, we need to know if our assemblies are “dirty.” By dirty, we mean littered with ions. Ions on printed circuit assembly surfaces can cause short circuits. In simple terms, shorts occur when the space between the conductors is bridged by dendrites formed by re-deposited metal ions (See Photograph 1). This metal migration is best described as a reverse plating of the conductors in the presence of ions, water and an electrical potential.2

Dentritic growth observed between parallel isolated circuitsPhotograph 1 Dentritic growth observed between parallel isolated circuits.

Electrochemical migration (ECM) failures can be difficult to isolate. Dendrites can form and disappear in a matter of minutes. These intermittent failures may cause disastrous outcomes. An intermittent short occurring on a printed circuit assembly (PCA) could cause a plane to crash or a heart/lung machine to stop.

If dendritic growth is suspected or observed on a field failure return, it is advisable to assess the risk of this failure occurring on the remainder of the product in the field. The steps outlined below are not the “best” way to evaluate the propensity of a process to develop leakage current because it is a reactive approach, but it can useful in estimating future risk.

  • Monitoring points connected to the area of concern are isolated, often by removing components or cutting other traces and wires are soldered.
  • The assemblies are placed in a temperature/humidity chamber and a bias is applied across the suspect location.
  • The resistance between these isolated points is monitored for sudden or slow drops that are indicative of leakage current development or dendritic growth.
  • If ECM development is observed on these assemblies from the same lot, the entire lot should be considered at risk.

A better way of assessing risk of leakage current development is through a preventive approach. The first step in reducing the risk of ECM failure is purchasing boards and components that are ionically “clean” and choosing soldering pastes and fluxes that meet the requirements of an international standard such as IPC J-STD-0043 and processing them correctly.

The second step in reducing the risk of ECM failure is assessing the assembly process. How likely is the combination of products used in the assembly process to develop leakage current in the field? Contract Manufacturers (CM’s) and/or Original Equipment Manufacturers (OEM’s) are tasked with the responsibility of performing this risk assessment. One way to evaluate the effectiveness of the assembly process is to recreate the exact steps they use in their processes and assess the product via an accelerated reliability test. Manufacturers may choose to evaluate their process using a Surface Insulation Resistance (SIR) test with temperature and humidity because they want to simulate the exposure of their product in the field. PCA’s are used in products that are exposed to environments that range from cold and dry to hot and moist, often fluctuating between the two.

Those companies on the forefront of product evaluation take SIR testing a step beyond the routine. With the printed circuit board industry moving to fine-pitched, low-clearance, lead-free products, the risk for ECM failure is ever increasing. Those companies in need of the most reliable PCA possible (IPC Class 3 High Performance Electronic Products) want to evaluate what effect these assembly changes will have on long term performance.

Reactive Approach - Two Case Studies

Dendritic growth has been observed or leakage current is suspected on a field failure return. Where should you start with determining the cause of the failure? The most common causes of leakage current development on printed circuit assemblies are the following:

  • Incoming printed circuit boards contained high levels of surface ionic contaminants and the boards were assembled using a no-clean process, hence leaving the board contaminants in place
  • Incoming components contained high levels of surface ionic contaminants and the components were assembled using a process that is cleaned, but contaminants are not washed away due to the low-clearance nature of the components4
  • Incoming components contain ionic contamination which is not washed away for reasons listed above
  • Unactivated flux remains on the board due to improper reflow program, inadequate washing, or sloppy rework process
  • A combination of products is present on the assembly that stimulates the development of leakage current

 

Case Study Number 1

A small OEM purchased components from one of their suppliers. Upon inspection, a contaminant was observed on the leads of the device. Once the components were soldered, the contaminant was still visible. The OEM was concerned that the contaminant, if left in place, could develop corrosion or leakage current. The component supplier reworked the components to the best of their ability, but there was still visible contamination present.

Because the contamination was observed prior to assembly, the study could be isolated to address the component problem alone. The footprint of the component was such that it could be soldered to a standard SIR test board (See Photograph 2). To best assess the potential for leakage current, clean IPC-B-25 were supplied to the OEM and they attached the components to the test boards using their standard assembly procedures.

Please note that this analysis does not assess the interaction that could occur between the PCB chemistry and the component chemistry, but because the boards were not yet assembled with the questionable components, scrap product could be minimized by utilizing standard test boards for the analysis. Additionally, in this case it is acceptable that the suspect location on the component see the heat of assembly as this is the process it will see prior to going out in the field. In case study 2, the importance of not adding additional heat following assembly will be addressed.

Positioning of component on standard test board used to assess leakage current developmentPhotograph 2 Positioning of component on standard test board used to assess leakage current development.

Because the boards were assembled using a no-clean process, a standard test environment of 40°C and 93%RH was chosen. Temperatures below 50°C should be used for no-clean low-solids soldering materials because the organic acid portion of the paste/flux will sublimate above this temperature. The test duration was 1008 hours. The bias voltage which was applied was 50 volts Direct Current (DC) with a measurement voltage also of 50 volts DC with the same polarity as the bias voltage. When internal component circuitry shorts the isolated circuits it must be removed from the circuit either by cutting the leads or removing the internal circuitry.

For the component assessment outlined above, the insulation resistance of the isolated circuits was monitored throughout the test. The data is presented below (see Figures 1 and 2).

Figure 1 Figure 1 Representative Insulation Resistance Values in Log Ohms

Figure 2Figure 2 Graphic Representation of IR Values in Ohms Exhibiting the Typical Bathtub-shaped curve with Evidence of Leakage Current Development

The data above is indicative of leakage current development in the areas that drop down in the 10P6P log ohm range. The typical bathtub curve was observed with IR values dropping during the first 24 hours of testing but remaining relatively consistent throughout the forty-two day exposure except for the two points indicated. A drop of one decade or more in resistance is indicative of leakage current development. A visual examination of the boards post-exposure showed carbonized debris which is indicative of a dendrite forming and burning off. Following this test, the customer decided that reworking the components was not an option and that they would move to an alternate source.

Case Study Number 2

A more common issue presented to a laboratory for assessment is the field failure return with a suspected electromigration failure. Assemblies or boards from the same lot will be required for the analysis. Please note that this procedure is not an industry-recognized procedure. In cases where no initial process validation was performed, an ECM failure has been observed, and there is no time to use standard process validation techniques, this method is the only option aside from a full product recall in the case of Class 2 or 3 high reliability product. The risk of not recalling the product is the sole responsibility of the OEM at this point, so a thorough risk assessment should be performed by the company’s Technical Review Board (TRB). In no way is the author guaranteeing reliability based on the outcome of these procedures. A TRB’s decision will vary depending on industry segment, the end item requirements, the end-use environment, consequences of failure and which aspect of reliability is being discussed. Acceptable risk for a cell phone may not be acceptable for an implantable medical device5.

The devices pictured below were submitted because an electrochemical migration failure on the lot was suspected. See Photos 3 and 4.

ECM Photo 3 ECM Test Sites Identified
Photograph 3 Boards submitted for evaluation of ECM potential. Photograph 4 Test sites identified.

In this case, the board supplier’s customer is questioning the cleanliness of their incoming bare boards, so bare boards are submitted for testing. The board supplier’s customer is seeing intermittent shorts on product in the field.

The first step in preparing a plan to assess ECM potential is to identify the locations where potential ECM has occurred. These sites should not be soldered to directly because the heat presented during the solder step could very easily eliminate the contaminant causing the failure. Instead, the artwork files should be used to track out to alternate sources for soldering that are away from the intended test site. Starting on the left in photo 4 above, large pad 2A runs internally to small pad 2A and large pad 2B runs to small pad 2B. By soldering to large pads 2A and 2B, we will be assessing the adjacent smaller pads, 2A and 2B. By soldering to the larger pads, soldering heat is kept away from the suspect location. Removal of components in order to isolate to parallel circuits is often required. Removal of components should be done by a mechanical means and should not disturb the suspect location.

Large pads 3A and 3B and large pads 1A and 1B also connect to their smaller counterparts. The samples were wired accordingly and placed within the temperature/humidity chamber. Initial ambient data was collected, and in this case, the customer elected to run a twenty-one day electromigration test at 65°C and 85%RH with a 10 VDC bias and measurement voltage. The data is outlined in Figure 3. Based on these electrical results and visual observations, it does not appear that a substance on the bare board in the suspect locations would have alone induced an ECM-type failure.

ECM Data Collected for Case Study 2Figure 3 ECM Data Collected for Case Study 2

Visual Examination ResultsFigure 4 Visual Examination Results for Case Study 2

 

Below, in Photographs 5 and 6, is another example of production printed circuit assemblies being assessed through applying temperature, humidity and bias to suspect test sites. The sites that are soldered below lead to other locations on this small two inch by three inch assembly used in the implantable medical industry.

Example of Fine Soldering Required Dendritic Growth Observed FOllowing Temp Humidity Exposure
Photograph 5 Example of Fine Soldering Required to Assess Products Such as Implantable Medical Products Photograph 6 Dendritic Growth Observed Following Temperature Humidity Exposure With Bias

Reactive Approach Conclusions

The reactive approach is not the optimum way to analyze the potential threat of electrochemical migration and leakage current which can lead to product short circuits. Because this is not an industry-accepted method and all aspects of the test are product specific, you cannot apply industry-accepted pass/fail criteria. For example, although a decade drop may not be observed during the test, results in the 10P7P ohm range may not be acceptable based on the product spacing and actual current application. The use of standard test boards with established pass/fail criteria is a better solution if you are in the position to take a preventive approach and are not already reacting to a failure returned from the field.

The Preventative Approach

What does it mean to take a preventive approach when it comes to assessing ECM potential? As was mentioned above, the first step in reducing the risk of ECM failure is purchasing boards and components that are ionically “clean” and choosing soldering pastes and fluxes that meet the requirements of an international standard such as IPC J-STD-004 and processing them correctly. This will require a bit of research and testing on the part of the CM or OEM.

If you choose soldering products that are purchased from reputable companies that are able to provide you actual data as it relates to meeting the J-STD-004 requirements, than process validation need only be performed. Please note that there are paste and flux manufacturers that will advertise their products meet the requirements of this or other international standards, but 10 years or more may have elapsed since the product was actually tested. As one can imagine, although it may be unintentional, raw materials and formulae will change over the years, so ongoing confirmation that the material is still classified as the same reactivity level is imperative.

The same holds true for the board and component suppliers. If only low level contamination is acceptable in your process due to tight spacing, low tolerances and need for high reliability, then these requirements should be spelled out on purchasing documents AND they should be periodically confirmed on incoming inspection. Although it is true that requirements specified on purchasing documents are binding and legal recourse could be taken if a cleanliness problem is discovered, product will already be in the field and a recall situation will be required. This expense would be much greater than the cost of initially confirming that the assembly process is under tight control. The way to keep the assembly process under control as it relates to cleanliness will be discussed below.

Assessing Cleanliness of the Assembly Process

IPC J-STD-001D, Appendix C6 contains information regarding assessing cleanliness of the assembly process as well as compatibility of the materials used within the process. This is assessed through a required Surface Insulation Resistance (SIR) test and optional ionic tests, Resistivity of Solvent Extract (ROSE) and Ion Chromatography (IC).

The current SIR recommended test vehicle is the IPC-B-36 board pictured in photograph 6 without components and in picture 7 with components.

IPC-B-36 Board Prior to Assembly IPC-B-36 Assembly with Dummy Components
Photograph 7 IPC-B-36 Board Prior to Assembly Photograph 8 IPC-B-36 Assembly with Dummy Components

There are ten test sites on this board (see Figure 5). Four of these are comb patterns, M1, M3, M5 and M8. The fingers of the comb patterns run perpendicularly to each other, so tha t entrapment of residues may be better assessed (i.e., the direction of the flow of cleaning, if cleaning takes place, will more easily rinse residues from one pattern versus the other). The spacing of the comb pattern is .0065 inches.

Test points M2 and M4 are daisy - chained pads. Every other pad is connected so that on patterns C and D below, the spot between every pad is being assessed. Dummy components, those with the circuitry removed, are applied to the test board and soldered to these pads. 68PLC C’s (plastic leadless chip carriers) are typically used for this test.

Test points M6, M7, M9 and M10 are perimeter patterns. They are not covered by the components and lie uncovered around the periphery of the component area. Because these areas are not covered, they are the easiest to clean.

Ten Test Points of the IPC-B-36 BoardFigure 5 Illustration Showing the Ten Test Points of the IPC-B-36 Board

Best Cleaning/Process Assessment

The most effective way to assess the “cleaning” process is to have your printed cir cuit board supplier manufacture the test boards using the same laminate, solder mask and plating chemistry that is typically used on your supplied product. The boards would then be assembled using the standard profiles that are used in your assembly proce ss. This should also include the addition of any rework materials that may be used in the process of manufacturing the product. This is the most effective way to assess the “cleaning” process. “Cleaning” is in quotations because this test procedure can be used to assess no - clean processes, as well. Trapped unreacted no - clean flux can as easily cause ECM as a non - rinsed aqueous - cleaned product.

Ten assemblies are prepared by the CM/OEM and submitted for testing. The boards are wired, placed in a temper ature/humidity chamber for 168 hours and monitored for the development of leakage current. If the boards are not conformally coated a static environment is used. If the boards are conformally coated, they may be tested in a condensing environment to conf irm the effective functioning of the coating.

Each “type” of cleaning challenge is assessed, the comb patterns, the pads and the periphery patterns. Based on the results, adjustments may be made to the assembly process and the test repeated. The test i s repeated until satisfactory results are obtained. This test may then be repeated periodically to confirm that the assembly process is still in control.

Assessing Cleaning Only

Often, the time and expense is too great or the risk low enough that a CM/OE M will decide to test their process only. In this case, standard FR4 boards with bare copper are used. These boards are cleaned prior to testing and then processed as usual. In this case, the board production chemistry and its interaction with the assem bly process chemicals are not being assessed.

IPC J-STD-001 Under Revision

The current J - STD - 001 Appendix C is currently under revision. It has been recognized that a single component style does not represent everyone’s process. Often the 0.004 inch sta ndoff is much more of a challenge for those trying to utilize this method than is typical of their assembly process. Bent leads and/or solder mask bumps are one way to adjust the IPC - B - 36 design to give a larger standoff. Additionally, J - STD - 001 does not specify that an assembler must use the standard board test board. They have the option of designing their own and proving the design an effective indicator, but is obvious that there is additional expense when using this option.

There is a new test boar d that is being analyzed. It is called the IPC - B - 52 board (see Photograph 8). This test board includes the following locations that have been specifically designed for SIR testing 7 :

  • Horizontal Connector
  • 0402 Capacitor Field
  • SM IEEE1386 Connector
  • 0805 Cap Fields
  • Ball Grid Array (BGA)
  • Quad Flat Pack (QFP) 160
  • QFP80
  • 0603 Cap Field
  • SOIC16 (U4 - U7)
  • 1206 Cap Field
  • Vertical Connector (J1)

IPC-B-52 Board

Photograph 9 IPC-B-52 Board

With all the options listed above as it relates to tests sites available, one ca n see how beneficial this standard test board will be. Studies are currently underway to establish pass/fail criteria for this new test board which will be incorporated in to the newest revision of J - STD - 001

Future Work

Future work will focus on forming an IPC task group to determine if a guideline document can be developed to assist CM’s and OEM’s who are in a reactive position. This document would require additional research and round robins to establish a suggested test protocol.

ACKNOWLEDGEMENTS

This author would like to acknowledge Debora Obitz, Elizabeth Allison and Michael Allison of Trace Laboratories - MD for their work in providing the data and photographs and the real - time dendritic growth video that will be shown during the presentation of t his paper.

Originally published in the proceedings of the Pan Pacific Microelectronics Symposium Kauai, Hawaii, February 2008.

REFERENCES

[1] IPC/ANSI J - STD - 001D, U Requirements for Soldered Electrical and Electronic Assemblies U , February 2005.
[2] U Elect rochemical Migration: Electrochemically Induced Failures in Printed Wiring Boards and Assemblies: IPC - TR - 476A U , 1984, Northbrook, IL, IPC.
[3] IPC/ANSI J - STD - 004, U Requirements for Soldering Fluxes U , January 2004.
[4] T. Munson, “Component Cleanliness in a No - Clean World”, U Circuits Assembly U , March 2003, pp. 58.
[5] D. Pauls, C. Slack, “ Process Qualification Using the IPC - B - 52 Standard Test Assembly”, Presented at IPC Printed Circuits Expo®, APEX® and the Designers Summit 2006.
[6] IPC/ANSI J - STD - 001D, U Requ irements for Soldered Electrical and Electronic Assemblies U , February 2005, Appendix C.
[7] D. Pauls, C. Slack, “ Process Qualification Using the IPC - B - 52 Standard Test Assembly”, Presented at IPC Printed Circuits Expo®, APEX® and the Designers Summit 2006